4509 Datasheet, PDF (53/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(Note 1)
Reset
Internal mode
A
Operating state
Operation source clock:
f(RING)
On-chip oscillator
POF instruction execution
(Note 5)
Key-on wakeup
(Note 6)
(MR0)←1
(Note 3)
(MR0)←0
(Note 2)
CRCK instruction no execution
B
Operating state
POF instruction execution
(Note 5)
Operation source clock: f(XIN)
Ceramic resonator: operating
D
Operating state
RAM back-up
(Note 4)
CRCK instruction execution
C
Operating state
Operation source clock: f(XIN)
RC oscillation
POF instruction execution
(Note 5)
High-speed mode
f(RING): stop
f(XIN): stop
Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times from system is released from reset.
2: When changing the operation source clock from f(RING) to f(XIN), first make the setting to enable f(XIN) oscillation (set MR1 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(XIN) (set MR0 to “0”).
After this, stop f(RING) (set RG0 to “1”). (Do not start f(XIN) oscillation and change the operation source clock at the same time.)
3: When changing the operation source clock from f(XIN) to f(RING), first make the setting to enable f(RING) oscillation (set RG0 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(RING) (set MR0 to “1”).
After this, stop f(XIN) (set MR1 to “1”). (Do not change the operation source clock and stop f(XIN) at the same time.)
4: After system is released from reset, the ceramic oscillation circuit is selected for the main clock f(XIN).
When the RC oscillation circuit is used, execute the CRCK instruction.
5: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state.
6: Microcomputer starts its operation after counting f(RING) 120 to 144 times.
System returns to state A certainly when returning from the RAM back-up mode. The operation mode (system clock frequency divided)
also returns to the initial state (internal frequency divided by 8 mode) (registers RG and MR initialized).
However, the selected contents (CRCK instruction execution state) of f(XIN) oscillation circuit is retained.
Fig. 46 State transition
EPOF ₊ POF
instruction instruction
Power down flag P
SQ
Reset input
R
q Set source • • • • • • • _{EPOF instruction + POF instruction}
q Clear source ^{• • • • • •}Reset input
SNTP
Program start
P = “1”
Yes
?
No
Cold start
Warm start
Fig. 47 Set source and clear source of the P flag
Fig. 48 Start condition identified example using the SNZP in-
struction
Rev.1.02 2006.12.22 page 53 of 140
REJ03B0147-0102