4509 Datasheet, PDF (46/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
Master
SOUT
SIN
SST instruction
M7’
S7’
M0
M1
M2
M3
M4
M5
M6
M7
S0
S1
S2
S3
S4
S5
S6 S7
SCK
Slave
SST instruction
SRDY signal
SOUT
SIN
S7’
M7’
S0
S1
S2
S3
S4
S5
S6
S7
M0
M1
M2
M3
M4
M5
M6 M7
M0–M7: Contents of master serial interface register
S0–S7: Contents of slave serial interface register
Rising of SCK: Serial input
Falling of SCK: Serial output
Fig. 39 Timing of serial interface data transfer
Table 16 Processing sequence of data transfer from master to slave
Master (transmission)
Slave (reception)
[Initial setting]
[Initial setting]
• Setting the serial interface control register J1 and inter- • Setting serial interface control register J1, and interrupt control register V2
rupt control register V2 shown in Figure 38.
shown in Figure 38.
TJ1A and TV2A instructions
TJ1A and TV2A instructions
• Setting the port received the reception enable signal • Setting the port transmitted the reception enable signal (SRDY) and output-
(SRDY) to the input mode.
ting “H” level.
(Port D3 is used in this example)
(Port D3 is used in this example)
SD instruction
SD instruction
* [Transmission enable state]
*[Reception enable state]
• Storing transmission data to serial interface register SI. • The SIOF flag is cleared to “0.”
TSIAB instruction
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Transmission]
[Reception]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
• Check reception completes.
SNZSI instruction
SNZSI instruction
•Wait (timing when continuously transferring)
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, control
the clock externally because serial transfer is performed as long as
clock is externally input. (Unlike an internal clock, an external clock
is not stopped when serial transfer is completed.) However, the
SIOF flag is set to “1” when the clock is counted 8 times after ex-
ecuting the SST instruction. Be sure to set the initial level of the
external clock to “H.”
Rev.1.02 2006.12.22 page 46 of 140
REJ03B0147-0102