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4509 Datasheet, PDF (25/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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4509 Group
(3) Notes on interrupts
â Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register
I1 in software, be careful about the following notes.
â Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the follow-
ing notes.
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register I1
is changed. In order to avoid the occurrence of an unexpected in-
terrupt, clear the bit 0 of register V1 to â0â (refer to Figure 18â) and
then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to â0â
after executing at least one instruction (refer to Figure 18â).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 18â).
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register I1
is changed. In order to avoid the occurrence of an unexpected in-
terrupt, clear the bit 0 of register V1 to â0â (refer to Figure 20â) and
then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to â0â
after executing at least one instruction (refer to Figure 20â).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 20â).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Control of INT pin input is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Interrupt valid waveform is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
â Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
â : these bits are not used here.
Fig. 20 External 0 interrupt program example-3
⢠When the INT pin input is disabled (register I13 = â0â), set the key-
on wakeup of INT pin to be invalid (register L10 = â0â) before
system enters to the RAM back-up mode. (refer to Figure 19â).
LA 0
TI1A
DI
EPOF
POF
; (âââ02)
; INT key-on wakeup disabled ........... â
; RAM back-up
â : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Rev.1.02 2006.12.22 page 25 of 140
REJ03B0147-0102
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