PT7A6632 Datasheet, PDF (8/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Table 2. Pin Description (Continued)
Pin
Name
Type
Descr iption
Attention: Active HIGH. A HIGH requires PT7A6632 to process the Channel Activation
57
ATTN
I Byte (CAB) at Activation Memory location xx00H in the shared memory. ATTN will be
deasserted in response to assertion of ATACK.
58
AS
O ^{Memory Address strobe: active LOW. Its falling edge will make a valid memory address}
be on the memory address lines.
59
INTR
O ^{Interrupt: active LOW. A LOW indicates that the buffer status byte is under update. Its}
pulse duration is equal to one SYSCLK period.
64
RSER
I ^{Received Serial Data: Serial data input line, receiving data bit stream from the T1/E1}
Interface.
Receive Red Alarm: A HIGH indicates the received data is invalid due to loss of
65
RRED
I frame alignment or similar reason. If so, PT7A6632 stops processing in all receive
channels until the reception synchronization restored.
66
RSYNC
I
Receive Synchronization: active HIGH. Level or pulse input for receive frame
synchronization.
67
RCLK
I
Receive Clock: Clock for serial data receiving. Input from the T1/E1 interface / clock
recovery circuit. Frequency is 1.544MHz for T1 or 2.048MHz for CEPT PCM-30.
TSER Enable: active HIGH, decides TSER line status along with FILL/MASK bit in
descriptor.
68
TSEREN
I
When TSEREN = 1, FILL/MASK = 1, send data on TSER,
FILL/MASK = 0, send a 1 on TSER.
When TSEREN = 0, FILL/MASK = 1, Send data on TSER,
FILL/MASK = 0, high impedance on TSER.
PT019(05/02)
8
Ver:2