PT7A6632 Datasheet, PDF (6/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Description
Table 2. Pin Description
Pin
Name
Type
Descr iption
1, 9, 43, 60,
63
NC
2
TMAX
3
SIS
4
RESET
5
T1/CEPT
6
HCS0
7
HCS1
8
CH0
10
CH1
11
CH2
12
CH3
13
CH4
14
Rx/Tx
15
TCLK
No connection
I
Tr ansmit multifr ame sync: pulse input from T1/E1 Trunk Interface, active HIGH.
Getting to high indicates the begining of a multiframe.
Serial interface select: decides the effective edge of TCLK and RCLK. See Table 25.
I
SIS = 1, falling edge of TCLK and RCLK effective.
SIS = 0, rising edge effective.
Reset: input for initializing the PT7A6632, active HIGH. The initialization will be
completed within 90 SYSCLK periods after RESET changes to LOW. The RESET sets
the device in the following state:
I
- HDLC mode,
- all the FILL/MASK bits are zeros,
- all channels deactivated,
- transmit channels output all ones.
I ^{Select T1 or CEPT mode: a HIGH sets the device in T1 framing mode, a LOW sets in}
CEPT PCM-30 framing mode.
Hyperchannel select: set standard hyperchannel patterns in T1 or CEPT mode:
- In T1 mode (T1/CEPT = 1),
HCS0 HCS1 = 01, four channels of 384 kb/s (H0),
= 10, single channel of 1.536Mb/s (H11).
I ^{- In CEPT PCM-30 mode (T1/CEPT = 0):}
HCS0 HCS1 = 01, single channel of 1.92Mb/s, time-slot 0 and 16 are 64kb/s (H12),
= 10, reserved.
- In any of T1 or CEPT PCM-30 mode,
HCS0 HCS1 = 00, all channels are 64kb/s,
= 11, reserved.
O
Channel number: indicates current active channel’s number (binary). CH0 is the LSB
and CH4 is the MSB.
O ^{Receive/transmit channel: indicates direction of current active channel. HIGH means}
receive and LOW means transmit.
Transmit clock: Square wave input from T1/E1 Trunk Interface. Used for PT7A6632
I transmit interface clock. Its phase must be aligned with that of SYSCLK and frequency
is one half of SYSCLK.
PT019(05/02)
6
Ver:2