PT7A6632 Datasheet, PDF (35/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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• MODE Byte (Channel Mode)
The Channel Mode Byte is set up by the CPU to specify channel modes of HDLC, non-HDLC signaling, non-HDLC data, loop,
non-loop, inversion or non-inversion.
The details are shown in Table 13.
Table 13. MODE Byte in Receive Command Buffer
MODE
Name
Descr iption
Bits 7 - 4
Not used
Bit 3
1 Invertion
INV
0 Non-invertion
Bit 2
LOOP
1 Loop channel
0 Non-loop channel
Non-HDLC data channel mode: used in modes 0 and 1 of DMI application. The 6632 check the
00
availability of the allocated buffer and writes received data to the buffer. The 6632 updates the filled
buffer status and asserts INTR, then moves to the next data buffer. The data receiving and writing
will continue until it is interrupted by an ATTN signal or no more buffer available.
Bit 1, Bit 0
SIG,
HDLC
HDLC data channel mode: The channel is an HDLC channel or an LAPD message-oriented
01
channel. The 6632 deformats the HDLC data -- 16-bit CRC-CCITT polynomial is used to calculate
FCS, and ABORT, Flags and inserted zeros are recognized, no special processing for the header
(address and control fields).
Non-HDLC signaling channel mode: used in DMI or G.732 application to receive the bit-oriented
10 signaling data without HDLC format. The received data are stored into data buffers in the way
shown in Table 14. The 6632 detects the multiframe alignment and reports if any error is found.
11 Reserved
PT019(05/02)
35
Ver:2