PT7A6632 Datasheet, PDF (18/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 17. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0
RRED
RSYNC
Proving Period 1 Proving Period 2
(≤ one full
(one full
multiframe)
multiframe)
Proving Period 3
(one full
multiframe)
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER _{Bit 6 Bit 7 Bit 8 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8}
RRED
RSYNC
Time-slot 31, last
frame of a
multiframe
Time-slot 0, first frame of the next
multiframe
• Loop Mode
Data Reception Order
When a receive channel is specified in Loop Mode, data to be
sent to the external memory is not from the external T1/E1
trunk interface, instead, it is fetched internally from an inter-
mediate buffer in the PT7A6632, in which the data was from a
loop mode transmit channel. Thus the data from the external
memory is feedback to external memory. Each time only one
transmit and one receive channel can be specified in Loop
Mode to guarantee normal operation. The transmit loop chan-
nel No. and receive loop channel No. are not necessarily iden-
tical. The Loop Mode does not support hyperchannel.
Reset the device will delete all Loop Mode.
• Logical Inversion
If a receive channel is set in inversion mode, the received data
will be inverted bit by bit when being processed, including
flag, ABORT and FCS bits.
The PT7A6632 writes received data bytes in the external
memory in the same order in which they are received in time.
For a certain channel, the first received byte is written at byte
address m, the second received at byte address m+1, and so on
as long as the buffer is not completely filled or an end-of-frame
is not reached. After the end of the frame or the end of the
buffer (whichever occurs first) is detected, the PT7A6632 writes
the next received data byte at the first allocated address of the
next available buffer.
The PT7A6632 writes the first received data bit of an octet at
the LSB (D0) position of the external buffer byte, the second
received data bit at the next to LSB position, and so on. The
last (8th) received data bit of an octet is written at the MSB
(D7) position of the data byte.
Reset the device will make all channel in inversion mode.
PT019(05/02)
18
Ver:2