PT7A6632 Datasheet, PDF (17/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 15. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1
RRED
RSYNC
Proving Period 1 Proving Period 2
(≤ one full
(one full
multiframe)
multiframe)
Proving Period 3
(one full
multiframe)
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
RRED
Bit 7 Bit 8 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
RSYNC
Time-slot 31, last
frame of a
multiframe
Time-slot 0, first frame of the next
multiframe
Figure 16. Receive Frame Synchronization Timing - T1 Mode, SIS = 0
RRED
RSYNC
Proving Period 1 Proving Period 2
(≤ one full
(one full
multiframe)
multiframe)
Proving Period 3
(one full
multiframe)
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
RRED
Bit 7 Bit 8 Bit F Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
RSYNC
Channel 24, last
frame of a
multiframe
Channel 1, first frame of the next
multiframe
PT019(05/02)
17
Ver:2