PT7A6632 Datasheet, PDF (34/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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• Descriptors
The first 8 bytes in the Receive Command Buffer is Descriptors that specifies Next Buffer Address, Data Length and Status
respectively. See Table 12 for the definition.
Table 12. Descriptors in Receive Command Buffer
Name
Descr iption
Next Buffer
Addr ess
16-bit address word pointing to next buffer for 6632 to access
Data Length
8-bit, decides the non-flexible-hyperchannel process or flexible hyperchannel process.
Data Length = 0, 1 or 2, only normal channel process,
Data Length > 2, there is hyperchannel process.
In flexible hyperchannel mode, the Data Length is read to decide how many additional channels to be added
to/remove from the hyperchannel, and the bytes contain the additional channel numbers are read to
add/remove the corresponding channels.
MPTY
Empty: 1-bit, the CPU sets it to show that the buffer is empty, i.e., command data is not ready. In this case
the 6632 will keep polling this bit until it is reset.The CPU resets this bit when the command data is ready.
6632 sets the bit to inform the CPU that it completes command processing in the buffer.
CMND
IVBA
Command: 1-bit, set by the CPU to indicate the buffer is a Command Buffer.
Invalid Buffer Address: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Rx channel will be deactivated until the channel
is re-activated by the CPU.
PT019(05/02)
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