PT7A6632 Datasheet, PDF (11/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 7. Transmit Frame Synchronization Timing - T1 Mode, SIS = 1
TCLK
TMAX
FILL/MASK*
TSEREN (Low)
TSER
Channel 24
Bit 7 Bit 8
Channel 1
Bit F Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
High Z
High Z
High Z
Data
Data Data Data
Data
TSEREN (High)
TSER
1
1
11
Data
Time Fill
Data Data Data
Time Fill
Data
* The F-bit time is processed as if the FILL/MASK = 0. However, this actual FILL/MASK does not apply to the F-bit.
Figure 8. Transmit Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1
TCLK
TMAX
FILL/MASK
Time-slot 31
Bit 7 Bit 8
Time-slot 0
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
TSEREN (Low)
TSER
High Z
High Z
High Z
Data
Data Data Data
Data
TSEREN (High)
TSER
1
1
11
Data
Time Fill
Data Data Data
Time Fill Data
PT019(05/02)
11
Ver:2