PT7A6632 Datasheet, PDF(41/61 Page) Pericom Semiconductor Corporation

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Data Sheet

PT7A6632 32-Channel HDLC Controller

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Channel Period for Memory Access

The PT7A6632 accesses the external memory for buffer man-

agement and data processing.

Normally, the T1/CEPT PCM-30 data flow requires that a byte

of data should be supplied for transmission and a byte of data

be taken from the receiving source within a single channel

period. So the PT7A6632 divides a channel period into 2

halves, the first half is Tx memory access period and the sec-

ond is Rx memory access period, 4 TCLK periods for each. In

the first half of channel period, the PT7A6632 reads command

information, descriptors information and transmission data

from the external memory for Tx channels, and in second half

of channel period, it reads command information, descriptors

information from external memory and write the received data

to the memory for Rx channels.

Typically, the PT7A6632 fetches a data byte from the memory

during Tx channel period m for transmission of the data byte

over channel m in the next appropriate Tx channel m, and the

PT7A6632 takes a data byte from the receiving circuit of chan-

nel j and will store the data into the external memory in the

next appropriate Rx channel period j. Then the PT7A6632

moves to process the next Tx channel (m+1) and Rx channel

(j+1). See Figure 31.

In each Tx or Rx memory access period, the PT7A6632 can

access external memory for data byte for once, or twice if the

descriptor reading is necessary, even more, three times if an

ATTN signal asserted by the CPU.

At the start of each half-channel period, the PT7A6632 first

outputs the channel number CH0 - CH4, and the channel di-

rection Rx/Tx of the current channel. After around half TCLK

period, the PT7A6632 asserts DMND to inform the external

memory that it will access it after 1 TCLK period from the

rising edge of DMND. Then the PT7A6632 asserts the AS strobe,

whose falling edge will make the address valid on the address

bus. The PT7A6632 sends out READ or WRITE strobe to read

data from the memory or write data into the memory during

low of the READ or WRITE. After finish memory access (1, 2

or 3 times access as applicable) and sets the DMND low to

inform end of memory access of this half-channel period. Dur-

ing the process, if the ATTN is asserted and the PT7A6632

accesses the Activation Memory, it will assert SYSACC and

negate it after Activation Memory access completed.

Address setup time, address hold time, data setup time and

data hold time are specified such that a wide variety of off-the-

shelf RAM devices may be used. The READ output from the

PT7A6632 may be used as an Output Enable (OE) input to the

RAM devices. Since the PT7A6632 uses its SYSCLK input to

generate various strobes for memory access, the access time

requirements are automatically scaled depending on the T1/

CEPT PCM-30 application.

Figure 31. Channel Period

One Channel Period for Memory Access

Tx Memory Access

Rx Memory Access

8 TCLK Periods

Channel

Period

Channel No.

Served

One Channel Period

for Memory Access

for Tx for Rx for Tx for Rx

m j m+1 j+1

PT019(05/02)

Ver:2

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