PT7A6632 Datasheet, PDF (43/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Memory Address Restrictions
Activation Memory Address -- The PT7A6632 judges the
channel start address for its invalidity immediately after it reads
the Activation Memory for the address in response to the ATTN
assertion. If the 16-bit address is found invalid, the channel
will be deactivated. The channel start address is thought in-
valid by the PT7A6632 when it is all zero or in form of FFFx.
Data/Command Buffer Address -- The PT7A6632 checks next
buffer address in each buffer. If found a next buffer address is
invalid, the PT7A6632 will set the channel inactive and set
the IVBA bit of the current buffer. The channel can be reacti-
vated only when CPU asserts the ATTN signal.
The 16-bit next buffer address is thought invalid by the
PT7A6632 if it is all zero or in form of FFFx, namely, the
address is valid when it is within 0001 to FFEF.
The PT7A6632 locates a descriptor byte or a data byte by
adding offset to a next buffer address read from last buffer. The
maximum address in a buffer is the address of the last byte. As
for 16-bit address lines, the addresses are restricted in the range
of 2¹⁶ - 1 (65,535), the last byte address in a buffer should meet
the following condition:
Figure 34. Interrupt Indication
Last byte address in a buffer = buffer start address + 7 (decimal)
of descriptor bytes + 12-bit data length or buffer size <= 65,535.
If the last byte address exceeds the restriction, the PT7A6632
will access memory locations not intended for the channel. All
the external memory addresses should be within one 64k byte
bank.
Interrupt Indication
At the rising edge of INTR, channel No. and status contents
can be shifted into the external FIFO. The INTR is asserted by
the PT7A6632 when PT7A6632 updates the status of a buffer.
After update, the PT7A6632 negates the INTR and at its rising
edge the channel No. and status are guaranteed to be valid on
the bus so that external FIFO can take the information, and the
actual address of the status byte is also be placed on the bus.
The PT7A6632 removes the interruption channel No. and buffer
status without waiting for acknowledge from the CPU. See
Figure 34.
The CPU can take the actual status byte address and it can
relocate the completed buffers within the 64k byte bank and
also cross-check against its own list of linked buffer addresses.
If all the buffer start addresses are divisible exactly by 8, they
can be derived from the STATUS byte addresses by setting the
three LSB addresses to zero.
INTR
1/2 TCLK Period
6632 Updates Status
Channel No. and Status
are valid on the bus
PT019(05/02)
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Ver:2