PT7A6632 Datasheet, PDF (16/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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• HDLC Mode
• Non-HDLC Signaling Mode
In HDLC mode, the Receive Processor detects flags, abort,
delete zero-bit, check the Frame Check Sequences (FCS), and
filters the time-fill bits by applying FILL/MASK byte to the
received data.
Reset the device will make all channels in HDLC mode.
• Non-HDLC Data Mode
In non-HDLC signaling mode, PT7A6632 detects the
multiframe alignment sequence. If the alignment sequence is
valid, the received data will be sent to the external memory; if
not, the data will not be sent to external memory until a valid
alignment sequence is detected. The loss of the multiframe
alignment will be reported to external memory. Any channel(s)
can be specified to receive bit-oriented signaling. This feature
is very useful in central office switching applications.
In this mode, received data are directly written into external
memory without deformating.
Figure 13. 32kb/s Subrate Operation - Single Receive Channel
T1/CEPT PCM-30 Serial Input
TS m in Frame n+1
TS m in Frame n
A1BCD111E1FGH111
Received Data
1 0 1 1 1 0 0 0 FILL/MASK
A B C D E F G H _{Assembled Data Byte}
MSB
LSB
Figure 14. Receive Frame Synchronization Timing - T1 Mode, SIS = 1
RRED
RSYNC
Proving Period 1 Proving Period 2 Proving Period 3
(≤ one full
(one full
(one full
multiframe)
multiframe)
multiframe)
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
RRED
Bit 7 Bit 8 Bit F Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
RSYNC
Channel 24, last
frame of a
multiframe
Channel 1, first frame of the next
multiframe
PT019(05/02)
16
Ver:2