PT7A6632 Datasheet, PDF (38/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Device Operation
Device Initialization
The device is initialized by RESET signal. Upon reset, all the
channels are set in the following states:
- the operation mode is HDLC, inversion, non-loop,
- FILL/MASK byte: 0000 0000,
- all channels are inactive,
- Flexible hyperchannels are disabled,
- no data transferred from the external memory or written to the
external memory.
The PT7A6632 monitors the TMAX, RSYNC and RRED sig-
nals and correspondingly reset the Transmit channel counter
and the Receive channel counter to ascertain the framing syn-
chronization.
Channel Initialization
Before asserting the ATTN, the CPU first allocates memory in
the external memory for a Command Buffer containing 8 bytes
of descriptors including Next Buffer Starting Address, Data
Length, Status, and 2 bytes of Mode and Fill/Mask. And a
chain of linked data buffers are set up by the CPU following
the command buffer, containing Next Buffer Start Address,
Buffer Size, Data Length, Status and Data bytes. Then the CPU
set up the Activation Memory containing channel No. to be
activated and channel direction, and Channel Starting Ad-
dress (pointers) in the external memory. Then the CPU sends
out the ATTN signal.
The PT7A6632 receives the ATTN, starting to access the Acti-
vation Memory (asserting SYSACC) for the Channel Number
and the channel start address, which will be stored internally
in the PT7A6632. PT7A6632 asserts the ATACK after comple-
tion the access, CPU negates the ATTN in response to the
ATACK, and PT7A6632 negates the ATACK in response to
negation of ATTN. The channel initialization is completed.
The process is illustrated in Figure 28.
The channels are initialized for preparing data transmission
and reception by CPU asserting the ATTN signal.
This process can be repeated for each channel to be initial-
ized. The PT7A6632 must make three activation memory ac-
cesses to complete the channel ATTN processing. The worst
case of time delay from ATTN assertion to ATACK assertion is
three T1/CEPT PCM-30 channel periods. The earliest is 1.5
channel period.
Figure 28. Channel Initialization
CPU
!
ATTN
"
#
External Memory
Channel Activation
Byte for Channel #m
ATACK
%
PT7A6632
Channel #m Start
$
Address
PT019(05/02)
! CPU prepares data buffer and writes to activation byte for a channel.
" CPU asserts ATTN.
% PT7A6632 responds to ATTN, reads channel number, Rx/Tx, Active/Inactive in
channel activation byte.
$ PT7A6632 find out the corresponding channel start address and read the start address
of the first buffer allocated for the channel.
# PT7A6632 informs task completion by asserting ATACK.
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