PT7A6632 Datasheet, PDF (19/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Memory Manager
State/Control Machine
The Memory Manager controls data flow between Transmit
Processor/Receive Processor and the external memory as shown
in Figure 18. CPU assigns the external memory into several
parts for activation information (Activation Memory) and data
processing information (Data Processing Memory) as shown
in Figure 20 in Section “External Memory Organization and
Definition”.
The State/Control Machine processes the device mode and
status. MDFS sets the memory location pattern, i.e., the even
addresses in external memory are for higher bytes (MDFS = 1)
or for lower bytes (MDFS = 0) of the Next Buffer Starting Ad-
dress, Buffer Size and Data Length respectively.
Figure 19
The Data Processing Memory is allocated to each transmit and
receive channel for data, command and status storage. The
CPU allocated enough memory in the buffers for the real-time
operation of transmit and receive with no data underrun or
overrun. The external memory is managed with minimal inter-
vention from the CPU.
To Rx and Tx Processors
& Memory Manager
State / Control Machine
5
CH0-
CH4
Rx/Tx
The CPU sends out an ATTN signal to command PT7A6632 to
access the Activation Memory that contains channel number
and channel starting address. The SYSACC signal is asserted
by PT7A6632 during accessing the Activation Memory. After
the access, the ATACK will be asserted.
The Data Processing Memory contains such information as
next buffer address, operation mode, buffer size, data length,
buffer status and HDLC frame completion status. They are set
up by CPU. PT7A6632 accesses the buffers and processes data
and update the status in the buffers after processing. DMND is
asserted by the PT7A6632 to inform other devices using the
memory bus that PT7A6632 will access the external memory
one TCLK period after rising edge of the DMND. INTR as-
serted when PT7A6632 updates the status byte in buffers.
The memory manager responds to CPU-initiated changes in the
operational modes of a channel or relocation of the allocated
buffers without affecting the operation of the other channels.
The timing for the memory access is generated from SYSCLK.
2
RESET UAEN MDFS HCS0-HCS1 T1/CEPT SIS
UAEN sets the Upper address lines (A8 - A15) in high imped-
ance (UAEN = 1) or in Low state (UAEN = 0) when accessing
Activation Memory. When the upper address lines in high im-
pedance, the CPU can drive them to any state during accessing
activation memory.
HCS0, HCS1 and T1/CEPT select T1 or CEPT PCM-30 mode
and hyperchannel (Table 3). SIS selects trigger edge of RCLK
and TCLK. TSEREN sets TSER output line state, i.e., sending
data, sending “1” or in high impedance (Table 4).
CH0 to CH4 and Rx/Tx are status outputs indicating the cur-
rent active channel number and direction. CH0 is LSB, CH4 is
MSB.
The main clock for PT7A6632 is generated by the State/Con-
trol Machine from SYSCLK.
Figure 18. Diagram of Memory Manager with External Memory and CPU
CPU
3
PT019(05/02)
External
Memory
A0-A15
D0-D7
READ
WRITE
AS
DMND
ATTN
ATACK, SYSACC, INTR
19
Memory
Manager
From Rx Bit-Level Processor
/ To Tx Bit-Level Processors
SYSCLK
PT7A6632
Ver:2