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PT7A6632 Datasheet, PDF (25/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Table 6. Descriptors in Transmit Data Buffer
Name
Next Buffer
Addr ess
Descr iption
16-bit address word, pointing to next buffer for 6632 to access
Buffer Size
12-bit, specifies byte number of memory locations allocated by the CPU for current buffer. The 6632 reads
the Buffer Size only when the Status (CF/P = 0) shows that the data buffer contains partial data. The 6632
will convert the Buffer Size to the actual number of data bytes in this buffer.
Flag Control: 1-bit, indicates if any additional flags (except the minimum one flag followed CRC for
HDLC format) to be appendixed after the (CRC+1 FLAG) of the HDLC data. If FC is reset by the CPU,
FC
it means no additional flag to be added. If set by the CPU, it means there will be additional flag(s) to be
added to the data. The number of the additional flag(s) is specified in the optional FLAG COUNT byte in
the Tx Data Buffer.
Flag Offset Count: 1-bit, meaningful only when FC = 1. If FO is set by the CPU, the Tx channel counts
the total number of intentionally inserted zeros based on HDLC protocol, then divides the counted results
FO
by 8.The quotient (called "Flag Offset") represents the number of non-data byte inserted in the data. The
6632 subtracts the Flag Offset from the FLAG COUNT, which was set without knowledge of the inserted
zeros. The resultant is the actual number of additional flags to be added to the data.
Data Length
12-bit, specifies the actual number of data bytes to be transmitted in the Tx Data Buffer. The 6632 reads
the Data Length only if the Status shows that the buffer contains the last byte of a frame (CF/P = 1).
MPTY
Empty: 1-bit, if set by the CPU, it means the buffer is empty, i.e., data is not ready for transmission. The
6632 will keep polling this bit until it is reset. The CPU resets this bit when the data is ready. 6632 sets
the bit to 1 once it completes data transmission in the buffer, and the CPU can reuses the empty locations.
CMND
CF/P
IVBA
UNDR
Command: 1-bit, when set by the CPU, it means the buffer is a Command Buffer. If reset by the CPU, it
is a Data Buffer.
Complete Frame/Partial Data Buffer: 1-bit, set by the CPU to show that the data buffer contains the last
byte of an HDLC framed data. Actual number of data bytes is specified by the Data Length (Max. Data
Length: 4095).
If it is reset by the CPU, it means the buffer contains partial data of a frame, and the rest data is in succeeding
buffer(s). The 6632 automatically turns to the next successding buffer. Actual number of data bytes is
specified by the Buffer Size (Max. Buffer Size: 4095).
For non-HDLC data, the bit should be 0 for continuously data transmission, otherwise data transmission
will be interrupted.
Invalid Buffer Address: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, i.e., such as
address of 16 zeros or in form of FFFx. In this case, the Tx channel will be deactivated and all-one bytes
be transmitted until the channel is re-activated by the CPU.
Underrun: 1-bit, the 6632 sets the bit if the current Tx channel runs out of data, e.g., when the 6632 finds
an invalid buffer address, an empty buffer, or a command buffer following a partial data buffer. If so, the
6632 will send out an ABORT code followed by Flags until the condition is cleared (if in HDLC mode),
or the 6632 will send out all-ones bytes repeatedly until the CPU sets up a valid non-empty data buffer (if
in non-HDLC mode).
PT019(05/02)
25
Ver:2