PT7A6632 Datasheet, PDF (27/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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• Descriptors
The first 8 bytes in the Transmit Command Buffer are Descriptors that specify Next Buffer Address, Data Length and Status
respectively. See Table 7 for the definition.
Table 7. Descriptors in Transmit Command Buffer
Name
Descr iption
Next Buffer
Addr ess
Data Length
16-bit address word, pointing to next buffer for 6632 to access
8-bit, decides the non-flexible-hyperchannel process or flexible hyperchannel process.
Data Length = 0, 1 or 2, only non-hyperchannel process,
Data Length > 2, there is hyperchannel process.
MPTY
Empty: 1-bit, the CPU sets it to show that the buffer is empty, i.e., command data is not ready. In this case
the 6632 will keep polling this bit until it is reset.The CPU resets this bit when the command data is ready.
6632 sets the bit to inform the CPU completion of command processing in the buffer.
CMND
CF/P
IVBA
Command: 1-bit, set by the CPU to indicate the buffer is a Command Buffer.
Complete Command Buffer /Par tial Command Buffer : 1-bit, set by the CPU to indicate that the
command buffer is a Complete Command Buffer. During the Complete Command Buffer processing, the
6632 will transmit an HDLC ABORT if it is in HDLC mode.
The CPU resets the CF/P bit to indicate a Partial Command Buffer (CF/P=0, CMND=1). In this case the
6632 will send HDLC flag or non-HDLC all-ones byte(s), then continue to process next buffer.
Invalid Buffer Address: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Tx channel will be deactivated and all-one bits be
transmitted until the channel is re-activated by the CPU.
PT019(05/02)
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