PT7A6632 Datasheet, PDF (39/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Data Transmission and Reception Operation
In transmission, the PT7A6632 reads the first command buffer
according to the channel start address, judges status of buffer,
fetches the MODE and FILL/MASK information for the chan-
nel, then it reads the Next Buffer Start Address in the current
buffer. It goes to the next buffer to get Data Length/Buffer
Size, and data bytes to send the data out in according to mode
specified and update the status if necessary. The PT7A6632
processes channel by channel in this way. See figure 29 for
example.
In receiving, the PT7A6632 reads the command buffer of a
channel to locates the CPU-allocated buffers for received data
storage, and stores the processed data into the data buffer and
write the Data Length. It updates the Status of the completed
buffer if necessary. See figure 30 for example.
Figure 29. Typical Linked Buffer Transmit Sequence
xx00
Activation
Memory
xx80
xx81
xx82
xx83
Tx CH0
Tx CH1
xxBE
xxBF
Tx CH31
1: ATTN goes high.
2: PT7A6632 reads activation byte (xx00).
3: PT7A6632 reads the first buffer s starting address (command
or data), then sets ATACK, & starts processing that buffer.
4: PT7A6632 resets ATACK after ATTN goes low.
5: PT7A6632 continues processing command or data buffers as
controlled by the status of each.
Next BF Addr.
Command
Modes
FILL/MASK
Command Buffer
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #1
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #2
Next BF Addr.
Buffer Size
MPTY=0
CF/P=0
Data Buffer #3
Next BF Addr.
Buffer Size
MPTY=0
CF/P=0
Data Buffer #4
Data Processing Memory
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #5
PT019(05/02)
39
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