PT7A6632 Datasheet, PDF (1/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Applications
• Provides up to 32 full-duplex HDLC/SDLC
channels
• Compatible with 1.544 Mb/s T1 and 2.048Mb/s
CEPT PCM-30 carrier format
• Provides on-board buffer memory management
• Supports standard hyperchannel configuration and
fully programmable hyperchannel configuration
• Provides on-board CRC-16, automatic flag and
zero insertion and deletion functions in HDLC
format
• Provides programmable tri-state outputs to T1/E1
serial interface and FILL/MASK, thus enabling up
to 8 devices connecting to a TDM bus
• Provides data rate adaptation functions
• Compatible with HDLC, SNA SDLC, X.25, X.75,
LAPB, and LAPD protocols
• Support non-HDLC signaling channels
• Single +5V power supply
• Package: 68-pin PLCC
• Primary rate interfaces
• Basic-rate D-channel controller
• Multi-channel HDLC interfaces
Introduction
The PT7A6632 HDLC controller operates at layer 2
(data link protocol level) of the Open Systems Inter-
connection (OSI) reference model. It supports HDLC
and ISDN implementations.
The PT7A6632 processes data transmitting and re-
ceiving on a T1 or E1 communication link. It con-
nects between the T1/E1 serial bus and an external
memory shared with CPU(s), multiplexing /
demultiplexing up to 32 fully-duplex high-speed data
channels.
It provides additional functions that support X.30 and
X.31 rate adaptation and fully flexible hyperchannels.
Figure 1. Application Diagram of PT7A6632
D0-D7
External
E1/T1
CPU
Shared
A0-A15
HDLC
Trunk
Memory
PT7A6632
Interface
T1/CEPT
PCM-30
Line
PT019(05/02)
1
Ver:2