PT7A6632 Datasheet, PDF (31/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Receive Data Buffer
• Data Bytes
The Receive Data Buffer contains 8 bytes of descriptors and j
bytes of user’s data as shown in Figure 26. The MDFS pin
decides the MS byte and LS byte locations (in even and odd
addresses).
• Descriptors
The first 8 bytes in the Receive Data Buffer are Descriptors
that specify Next Buffer Address, Buffer Size, Data Length and
Status respectively. See Table 11 for the definition.
Following the Descriptors are received data. The number of
data bytes are indicated by Data Length which is written by
the PT7A6632 after it receives the last byte of an HDLC frame
or the HDLC ABORT code, upon the loss of multiframe align-
ment error from a non-HDLC signaling channel, or when Re-
ceiver Bit-Level Processor detects receive synchronization
error caused by RSYN, elastic buffer error or RRED. When it is
a partial data buffer, the number of data bytes is indicated by
the Buffer Size.
Figure 26. Receive Data Buffer
(Address) 7
(Contents)
0
i msb
i+1
Next Buffer
lsb ^Address
i+2
Not used
msb
i+3
i+4
Not used
msb
i+5
Buffer
lsb ^{Size (k)}
Data
lsb ^{Length (j)}
i+6
i+7
(i+7)+1
Not Used by PT7A6632
- _{OVER IVBA ABRT FCER SHER}
CF/P
CMND
(0)
MPTY
Status
First Date Byte
(i+7)+2
Second Date Byte
~~
~~
(i+7)+j
Last Date Byte
~~
~~
(i+7)+k
Last Location in Buffer
a. MDFS = 1
(Address) 7
(Contents)
0
i
i+1 _msb
lsb _{Next Buffer}
Address
i+2
i+3
Not used
msb
lsb _Buffer
Size (k)
i+4
lsb _Data
i+5
Not used
msb
Length (j)
i+6
- _{OVER IVBA ABRT FCER SHER}
CF/P
CMND MPTY
(0)
Status
i+7
Not Used by PT7A6632
(i+7)+1
(i+7)+2
First Date Byte
Second Date Byte
~~
~~
(i+7)+j
Last Date Byte
~~
~~
(i+7)+k
Last Location in Buffer
b. MDFS = 0
PT019(05/02)
31
Ver:2