PT7A6632 Datasheet, PDF (32/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Table 11. Descriptors in Receive Data Buffer
Name
Next Buffer
Addr ess
Descr iption
16-bit address word, pointing to next buffer for 6632 to access
Buffer Size
12-bit, specifies byte number of memory locations allocated by the CPU for current buffer. The 6632 reads
the Buffer Size when writes data into the buffer.
Data Length
12-bit, the actual number of data bytes received by 6632, written by the 6632 after it receives the last byte
of an HDLC frame or the HDLC ABORT code, or upon the loss of multiframe alignment error from a
non-HDLC signaling channel. DATA LENGTH is not written if the end of the allocated buffer is reached
before the last byte is received (i.e., if data frame length is greater than buffer size). In such a case, the
actual data length is equal to the given buffer size. Also, data length may not be written if the ATTN input
is asserted, resulting in the deactivation or reactivation of an active channel.
MPTY
DATA LENGTH will not exceed the programmed buffer size.
Empty: 1-bit, if set by the CPU, it means the buffer is empty, i.e., the buffer is ready for storing received
data. The PT7A6632 resets this bit when the buffer is not empty. The PT7A6632 will keep polling this bit
until it is set. The 6632 resets the bit whenever it updates the status.
CMND
Command: 1-bit, when set by the CPU, it means the buffer is a Command Buffer. If reset by the CPU, it
is a Data Buffer.
CF/P
ABRT
FCER
SHER
IVBA
OVER
Complete Frame/Partial Data Buffer: 1-bit, set by the 6632 to show that the data buffer contains the last
byte of an HDLC framed data or that synchronization is wrong. It will also be set by the 6632 if the HDLC
data or non-HDLC data receiving is aborted by re-synchro condition of ABORT, RRED, RSYNC or TMAX.
The 6632 resets this bit when the last byte of an HDLC frame is not in this buffer and 6632 will store more
data to the succeeding buffer. This bit will always be reset for non-HDLC mode or signaling mode.
Abor t, Fr ame Check Er ror, Shor t HDLC Fr ame Er ror : These 3 bits are used to report abnormal
conditions detected by 6632.
ABRT FCER SHER = 0 0 0: no errors detected,
0 0 1: short or non-integer HDLC frame error,
0 1 0: CRC error,
0 1 1: CRC error & non-integer error,
1 0 0: HDLC ABORT code received,
1 0 1: non-HDLC multiframe alignment lost,
1 1 0: elastic buffer error & RSYNC error,
1 1 1: RRED alarm.
Invalid Buffer Address: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Rx channel will be in idle state and not receive
more data until the channel is re-activated by the CPU.
Overrun: 1-bit, the 6632 sets this bit when the next empty data buffer is not available for received data
before a frame is completed in HDLC data receiving, or when the next empty data buffer is not available
for non-HDLC data receiving.
No overrun reported for signaling channel. New data will be written in place of earlier received signaling
data.
PT019(05/02)
32
Ver:2