PT7A6632 Datasheet, PDF (50/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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AC Characteristics
(Note: All output AC timing measurements are referenced to the 0.4V for low level and 2.4V for high level, and all input AC
timing measurements are referenced to the 0.8V for low level and 2.0V for high level.)
Serial Interface
• Transmit Frame Synchronization Timing
Table 18. Transmit Frame Synchronization Timing
Sym
Descr iption
Test Conditions
t_MS
TMAX Setup Time
t_MH
TMAX Hold Time
Min
Typ
Max Units
50
ns
50
ns
Figure 44. Diagram of Transmit Frame Synchronization Timing (SIS = 1)
TCLK
TMAX
(From T1/E1 Controller)
TSER
(From PT7A6632)
t t _MS
MH
BIT 8, CH24
F BIT
a. Transmit Serial Output - T1 Mode, TSEREN=1
BIT 1, CH1
TCLK
TMAX
(From T1/E1 Controller)
TSER
(From PT7A6632)
t t _MS
MH
BIT 8, CH24
F BIT
b. Transmit Serial Output - T1 Mode, TSEREN=0
BIT 1, CH1
TCLK
TMAX
(From T1/E1 Controller)
t t _MS
MH
TSER
(From PT7A6632)
BIT 7, TS31
BIT 8, TS31
BIT 1, TS0
BIT 2, TS0
c. Transmit Serial Output - CEPT PCM-30 Mode, TSEREN=0 or 1
PT019(05/02)
50
Ver:2