PT7A6632 Datasheet, PDF (4/61 Pages) Pericom Semiconductor Corporation – PT7A6632 32-Channel HDLC Controller

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Block Diagram
Figure 2. Block Diagram of PT7A6632
16
A0-A15
8
D0-D7
READ
WRITE
AS
DMND
ATTN
ATACK
SYSACC
INTR
Memory
Manager
Receive
Bit-Level
Processor
Transmit
Bit-Level
Processor
5
State / Control Machine
2
RSER
RSYNC
RRED
RCLK
TCLK
TSER
TMAX
TSEREN
SYSCLK
CH0-CH4
Rx/Tx
RESET ^{UAEN MDFS} HCS0-HCS1 T1/CEPT SIS
Pin Information
Pin Assignment
Table 1. Pin Assignment
Gr oup
Memory Interface
Serial Interface
CPU Interface
State & Control
Power
PT019(05/02)
Symbol
Function
D0-D7, A0-A15, READ, WRITE, AS, Data, Addresses & Signals with Shared
DMND
Memory
RSER, RSYNC, RRED, TSER, TMAX,
SYSCLK, TCLK, RCLK, TSEREN
Data & Timing with Serial Interface
ATTN, ATACK, SYSACC, INTR
Signals with CPU
SIS, T1/CEPT, HCS0, HCS1, MDFS,
UAEN, RESET, CH0-CH4, Rx/Tx
Device Status & Control Signals
V_CC, GND
Power & Ground
4
Ver:2