JN516X Datasheet, PDF (64/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

19.3.3 Two-wire Serial Interface
SIF_D
t_F
SIF_CLK
S
t_LOW
t_R
t_SU;DAT
t_HD;STA
t_SP
t_R
t_BUF
t_HD;STA
t_HD;DAT
t_F t_SU;STA
Sr
t_HIGH
Figure 43: Two-wire Serial Interface Timing
t_SU;STO
P
S
Parameter
Symbol
Standard Mode
Min
Max
Fast Mode
Unit
Min
Max
SIF_CLK clock frequency
fSCL
0
100
0
400 kHz
Hold time (repeated) START condition.
tHD:STA
4
-
0.6
-
µs
After this period, the first clock pulse is
generated
LOW period of the SIF_CLK clock
tLOW
4.7
-
1.3
-
µs
HIGH period of the SIF_CLK clock
tHIGH
4
-
0.6
-
µs
Set-up time for repeated START condition
tSU:STA
4.7
-
0.6
-
µs
Data setup time SIF_D
tSU:DAT
0.25
-
0.1
-
µs
Rise Time SIF_D and SIF_CLK
tR
-
1000 20+0.1Cb 300
ns
Fall Time SIF_D and SIF_CLK
tF
-
300 20+0.1Cb 300
ns
Set-up time for STOP condition
tSU:STO
4
-
0.6
-
µs
Bus free time between a STOP and START
tBUF
4.7
-
1.3
-
µs
condition
Pulse width of spikes that will be
suppressed by input filters (Note 1)
tSP
-
60
-
60
ns
Capacitive load for each bus line
Cb
-
400
-
400
pF
Noise margin at the LOW level for each
connected device (including hysteresis)
Vnl
0.1VDD
-
0.1VDD
-
V
Noise margin at the HIGH level for each
connected device (including hysteresis)
Vnh
0.2VDD
-
0.2VDD
-
V
Note 1: This figure indicates the pulse width that is guaranteed to be suppressed. Pulse with widths up to 125nsec
may also get suppressed.
19.3.4 Wakeup Timings
Parameter
Min
Typ
Max Unit
Notes
Time for crystal to stabilise
0.74
ready to run CPU
ms Reached oscillator amplitude
threshold. Default bias current
Time for crystal to stabilise
1.0
ms
ready for radio activity
Wake up from Deep Sleep
170
or from Sleep
µs Time to CPU release
Start-up time from reset
180
RESETN pin, BOR or
SVM
Wake up from CPU Doze
0.2
mode
µs Time to CPU release
µs
64
JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013