JN516X Datasheet, PDF (41/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

1
2
3
N
1
2
3
N
Conversion cycle 1
2¹⁷
Conversion cycle 2
Figure 28: Return To Zero Mode in Operation
12
3
N
12
3
N
Conversion cycle 1 ₂16 Conversion cycle 2
Figure 29: Non-Return to Zero Mode
11.1.5 Example Timer/Counter Application
Figure 30 shows an application of the JN516X timers to provide closed loop speed control. PWM1 is configured in
PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls
the power in the DC motor.
Timer 0 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the
tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application
software executing the control algorithm.
If required for other functionality, then the unused IO associated with the timers could be used as general purpose
DIO.
+12V
1N4007
JN516x
PWM1
Timer0
CLK/GATE
CAPTURE
PWM
M
Tacho
IRF521
1 pulse/rev
Figure 30: Closed Loop PWM Speed Control Using JN516X Timers
11.2 Tick Timer
The JN516X contains a hardware timer that can be used for generating timing interrupts to software. It may be used
to implement regular events such as ticks for software timers or an operating system, as a high-precision timing
reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include:
• 32-bit counter
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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