JN516X Datasheet, PDF (50/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

JN516x
DIO14
SI
F
DIO15
SIF_CLK
SIF_D
R_P
R_P
VDD
Pullup
Resistors
D1_I
N
CLK1_I
N
CLK1_OUT
D1_OUT
DEVICE 1
D2_I
N
D2_OUT
CLK2_I
N
CLK2_OUT
DEVICE 2
Figure 34: Connection Details
15.2 Clock Stretching
Slave devices can use clock stretching to slow down the read transfer bit rate. After the master has driven SIF_CLK
low, the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is
greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait
states.
SIF_CLK
Clock held low
by Slave
Master SIF_CLK
SIF_CLK
Slave SIF_CLK
SIF_CLK
Wired-AND SIF_CLK
Figure 35: Clock Stretching
15.3 Master Two-wire Serial Interface
When operating as a master device, it provides the clock signal and a prescale register determines the clock rate,
allowing operation up to 400kbit/s.
Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for
indicating when start, stop, read, write and acknowledge control should be generated. Write data written into a
transmit buffer will be written out across the two-wire interface when indicated, and read data received on the
interface is made available in a receive buffer. Indication of when a particular transfer has completed may be
indicated by means of an interrupt or by polling a status bit.
The first byte of data transferred by the device after a start bit is the slave address. The JN516x supports both 7-bit
and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address
will respond by returning an acknowledge bit.
The master interface provides a true multi-master bus including collision detection and arbitration that prevents data
corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure
determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus
affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices
to count off their low period. Once the clock input of a device has gone low, it will hold the SIF_CLK line in that state
until the clock high state is reached when it releases the SIF_CLK line. Due to the wired-AND connection, the
SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the
shortest high period.
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013