JN516X Datasheet, PDF (45/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

13 Serial Communications
The JN516x has two Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These
provide similar operating features to the industry standard 16550A device operating in FIFO mode. The interfaces
perform serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from
the CPU to external devices. In both directions, a configurable FIFO buffer (with a default depth of 16-bytes) allows
the CPU to read and write multiple characters on each transaction. This means that the CPU is freed from handling
data on a character-by-character basis, with the associated high processor overhead. The UARTs have the following
features:
• Emulates behaviour of industry standard NS16450 and NS16550A UARTs
• Configurable transmit and receive FIFO buffers (with default depths of 16-bytes for each), with direct access
to fill levels of each. Adds/deletes standard start, stop and parity bits to or from the serial data
• Independently controlled transmit, receive, status and data sent interrupts
• Optional modem flow control signals CTS and RTS on UART0.
• Fully programmable data formats: baud rate, start, stop and parity settings
• False start bit detection, parity, framing and FIFO overrun error detect and break indication
• Internal diagnostic capabilities: loop-back controls for communications link fault isolation
• Flow control by software or automatically by hardware
Internal
Interrupt
Interrupt
Logic
RTS
CTS
Modem
Signals
Logic
Interrupt
ID
Register
Interrupt
Enable
Register
Modem
Status
Register
Modem
Control
Register
Divisor
Latch
Registers
Baud Generator
Logic
Line
Status
Register
Line
Control
Register
Receiver
Logic
Receiver FIFO
Receiver Shift
Register
RXD
FIFO
Control
Register
Transmitter FIFO
Transmitter
Logic
Transmitter Shift
TXD
Register
Figure 32: UART Block Diagram
The serial interfaces contain programmable fields that can be used to set number of data bits (5, 6,7 or 8), even, odd,
set-at-1, set-at-0 or no-parity detection and generation of single or multiple stop bit, (for 5 bit data, multiple is 1.5 stop
bits; for 6, 7 or 8 data bits, multiple is 2 bits).
The baud rate is programmable up to 1Mbps, standard baud rates such as 4800, 9600, 19.2k, 38.4k etc. can be
configured.
For applications requiring hardware flow control, UART0 provides two control signals: Clear-To-Send (CTS) and
Request-To-Send (RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data.
RTS is an indication sent by the UART to the external device that it is ready to receive data. RTS is controlled from
software, while the value of CTS can be read. Monitoring and control of CTS and RTS is a software activity, normally
performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate
to software the state of the UART external interfaces. Alternatively, the Automatic Flow Control mode can be set
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
45