JN516X Datasheet, PDF (37/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

10.2 Serial Peripheral Interface Slave
The Serial Peripheral Interface (SPI) Slave Interface allows high-speed synchronous data transfer between the
JN516x and a peripheral device. The JN516x operates as a slave on the SPI bus and an external device, connected
to the SPI bus operates as the master. The pins are different from the SPI master interface and are shown in the
following table.
Signal
SPISCLK
SPISMISO
SPISMOSI
SPISSEL
DIO Assignment
Standard pins Alternative pins
DIO15
DIO13
DIO17
DIO12
DIO16
DIO14
Table 4: SPI Master IO
The SPI bus employs a simple shift register data transfer scheme, with SPISSEL acting as the active low select
control. Data is clocked out of and into the active devices in a first-in, first-out fashion allowing SPI devices to
transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the
clock signal SPICLK generated by the external master.
The SPI slave includes the following features:
• Full-duplex synchronous data transfer
• Slaves to external clock up to 4MHz
• Supports 8 bit transfers (MSB first), with SPISSEL deasserted between each transfer
• Internal FIFO upto 255 bytes for transmit and receive
• Standard SPI mode 0, data is sampled on positive clock edge
• Maskable interrupts for receive not empty, tx empty, rx above threshold, tx below threshold, tx overflow, rx
underflow, tx underflow, rx timeout
• Programmable receive timeout timer so that if data is in the receive FIFO but not above fill level and then
no further data arrives an interrupt can be created to allow the data to be read
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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