JN516X Datasheet, PDF (36/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

If more than one SPISEL line is to be used in a system they must be used in numerical order starting from SPISEL0.
A SPISEL line can be automatically de-asserted between transactions if required, or it may stay asserted over a
number of transactions. For devices such as memories where a large amount of data can be received by the master
by continually providing SPICLK transitions, the ability for the select line to stay asserted is an advantage since it
keeps the slave enabled over the whole of the transfer.
A transaction commences with the SPI bus being set to the correct configuration, and then the slave device is
selected. Upon commencement of transmission (1 to 32 bits) data is placed in the FIFO data buffer and clocked out,
at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same
number of data bits is being received from the slave as it transmits. The data that is received during this transmission
can be read (1 to 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be
sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction
has completed or alternatively the interface can be polled.
If a slave device wishes to signal the JN516X indicating that it has data to provide, it may be connected to one of the
DIO pins that can be enabled as an interrupt.
Figure 24 shows a complex SPI transfer, reading data from a FLASH device that can be achieved using the SPI
master interface. The slave select line must stay low for many separate SPI accesses, and therefore manual slave
select mode must be used. The required slave select can then be asserted (active low) at the start of the transfer. A
sequence 8 and 32 bit transfers can be used to issue the command and address to the FLASH device and then to
read data back. Finally, the slave select can be deselected to end the transaction.
SPISEL
SPICLK
SPIMOSI
SPIMISO
Instruction Transaction
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
Instruction (0x03)
24-bit Address
23 22 21
MSB
3210
Read Data Bytes Transaction(s) 1-N
SPISEL
0
1
2
3
4
5
67
8
9 10
SPICLK
8N-1
SPIMOSI
value unused by peripherals
SPIMISO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Byte 1
Byte 2
3
2
1
0
LSB
Byte N
Figure 24: Example SPI Waveforms – Reading from FLASH Device using Mode 0
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013