JN516X Datasheet, PDF (22/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

VDD
R1 18k
C1 470nF
JN516x
RESETN
Figure 11: External Reset Generation
The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin but are not
neccessary.
6.2 External Reset
An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width
will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The
JN516X is held in reset while the RESETN pin is low. When the applied signal reaches the Reset Threshold Voltage
(VRST) on its positive edge, the internal reset process starts.
The JN516x has an internal 500kΩ pull-up resistor connect to the RESETN pin. The pin is an input for an external
reset only. By holding the RESETN pin low, the JN516x is held in reset, resulting in a typical current of 6uA.
RESETN pin
Reset
Internal Reset
Figure 12: External Reset
6.3 Software Reset
A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the
RAM contents. For example this can be executed within a user’s application upon detection of a system failure.
6.4 Supply Voltage Monitor (SVM)
An internal Supply Voltage Monitor (SVM) is used to monitor the supply voltage to the JN516x; this can be used
whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be
detected and can be used to cause the JN516x to perform a chip reset. Equally, dips in the supply voltage can be
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013