JN516X Datasheet, PDF (34/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

10 Serial Peripheral Interface
10.1 Serial Peripheral Interface Master
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN516x and
peripheral devices. The JN516x operates as a master on the SPI bus and all other devices connected to the SPI are
expected to be slave devices under the control of the JN516x CPU. The SPI includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Programmable bit rates (up to 16Mbit/s)
• Programmable transaction size up to 32-bits
• Standard SPI modes 0,1,2 and 3
• Manual or Automatic slave select generation (up to 3 slaves)
• Maskable transaction complete interrupt
• LSB First or MSB First Data Transfer
• Supports delayed read edges
16 MHz
Clock
Divider
Data Buffer
SPI Bus
Cycle
Controller
SPICLK
SPIMISO
SPIMOSI
Select
Latch
SPISEL [2..0]
Figure 22: SPI Block Diagram
The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices
in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously. Master-Out-Slave-In or
Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN516X.
The JN516X provides three slave selects, SPISEL0 to SPISEL2 to allow three SPI peripherals on the bus. SPISEL0
is accessed on DI019. SPISEL1 is accessed, depending upon the configuration, on DIO0 or DIO14. SPISEL2 is
accessed on DIO1 or DIO15. This is enabled under software control. The following table details which DIO are used
for the SPISEL signals depending upon the configuration.
Signal
SPISEL1
SPISEL2
SPICLK
SPIMISO
SPIMOSI
SPISEL0
DIO Assignment
Standard pins Alternative pins
DIO0
DIO14
DIO1
DIO15
DO0
DO1
DIO18
DIO19
Table 2: SPI Master IO
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013