JN516X Datasheet, PDF (39/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

The clock source for the Timer0 unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler
where a value of 0 leaves the clock unmodified and other values divide it by 2 ^prescale value. For example, a prescale
value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz.
The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the gate function is selected,
then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers.
The following table details which DIO are used for timer0 and the PWM depending upon the configuration.
Signal
DIO Assignment
Standard pins Alternative pins
TIM0CK_GT
TIM0CAP
TIM0OUT
DIO8
DIO9
DIO10
DIO2
DIO3
DIO4
PWM1
PWM2
PWM3
PWM4
DIO11
DIO12
DIO13
DIO17
DIO5
DIO6
DIO7
DIO8
Table 5: Timer and PWM IO
The alternative pin locations can be configured separately for each counter/timer under software control, without
affecting the operation or location of the others If operating in timer mode, it is not necessary to use any of the DIO
pins, allowing the standard DIO functionality to be available to the application.
11.1.1 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode, as used by PWM timers 1,2 3 and 4 and optionally by Timer0, allows the user
to specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot
or as a train of pulses with a repetition rate determined by the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent
16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall
registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches
the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset
and the cycle repeats. If either the cycle time or low periods are changed while in continuous mode, the new values
are not used until a full cycle has completed. The PWM waveform is available on PWM1,2,3,4 or TIM0OUT when the
output driver is enabled.
Rise
Fall
Figure 26 PWM Output Timings
11.1.2 Capture Mode
The capture mode can be used to measure the time between transitions of a signal applied to the capture input
(TIM0CAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is
stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register.
The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon
reading the capture registers the counter is stopped. The values in the High and Low registers will be updated
whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the
mode was started. Therefore, if multiple pulses are seen on TIM0CAP before the counter is stopped only the last
pulse width will be stored.
© NXP Laboratories UK 2013
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