JN516X Datasheet, PDF (31/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

8.3.3 Auto Acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge
packet within a very short window after the transmitted frame has been received. The JN516x baseband processor
can automatically construct and send the acknowledgement packet without processor intervention and hence avoid
the protocol software being involved in time-critical processing within the acknowledge sequence. The JN516x
baseband processor can also request an acknowledge for packets being transmitted and handle the reception of
acknowledged packets without processor intervention.
8.3.4 Beacon Generation
In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition
rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data
delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU
intervention.
8.3.5 Security
The transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm is
handled by the security coprocessor and the stack software. The application software must provide the appropriate
encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same
time as the rest of the frame data and setup information.
8.4 Security Coprocessor
The security coprocessor is available to the application software to perform encryption/decryption operations. A
hardware implementation of the encryption engine significantly speeds up the processing of the encrypted packets
over a pure software implementation. The AES library for the JN516x provides operations that utilise the encryption
engine in the device and allow the contents of memory buffers to be transformed. Information such as the type of
security operation to be performed and the encrypt/decrypt key to be used must also be provided.
Processor
Interface
AES
Block
Encryption
Controller
AES
Encoder
Figure 20: Security Coprocessor Architecture
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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