JN516X Datasheet, PDF (21/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

6 Reset
A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the
reset vector. The reset process that the JN516x goes through is as follows.
When power is first applied or when the external reset is released, the High-Speed RC oscillator and 32MHz crystal
oscillator are activated. After a short wait period (13µsec approx) while the High-Speed RC starts up, and so long as
the supply voltage satisfies the default Supply Voltage Monitor (SVM) threshold (2.0V+0.045V hysteresis), the
internal 1.8V regulators are turned on to power the processor and peripheral logic. The regulators are allowed to
stabilise (about 15us) followed by a further wait (150usec approx) to allow the Flash and EEPROM bandgaps to
stabilise and allow their initialisation, including reading the user SVM threshold from the Flash. This is applied to the
SVM and, after a brief pause (approx 2.5usec), the SVM is checked again. If the supply is above the new SVM
threshold, the CPU and peripheral logic is released from reset and the CPU starts to run code beginning at the reset
vector. This runs the bootloader code contained within the flash, which looks for a valid application to run, first from
the internal flash and then from any connected external serial memory over the SPI Master interface. Once found,
required variables are initialised in RAM before the application is called at its AppColdStart entry point. More details
on the bootloader can be found in the application note - Boot Loader Operation. [8]
The JN516x has five sources of reset:
• Internal Power-on / Brown-out Reset (BOR)
• External Reset
• Software Reset
• Watchdog timer
• Supply Voltage detect

Note: When the device exits a reset condition, device operating
parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, then the device must be held in
reset until the operating conditions are met. (See Section 19.3)
6.1 Internal Power-On / Brown-out Reset (BOR)
For the majority of applications the internal power-on reset is capable of generating the required reset signal. When
power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD
reaches the specified threshold, the reset signal is generated. This signal is held internally until the power supply and
oscillator stabilisation time has elapsed, when the internal reset signal is then removed and the CPU is allowed to
run.
The BOR circuit has the ability to reject spikes on the VDD rail to avoid false triggering of the reset module. Typically
for a negative going square pulse of duration 1uS, the voltage must fall to 1.2v before a reset is generated. Similarly
for a triangular wave pulse of 10us width, the voltage must fall to 1.3v before causing a reset. The exact
characteristics are complex and these are only examples.
VDD
Internal RESET
Figure 10: Internal Power-on Reset
When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. If necessary, use of the
external reset circuit show in Figure 11 is suggested.
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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