JN516X Datasheet, PDF (51/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

Start counting
low period
SIF_CLK1
SIF_CLK2
SIF_CLK
Start counting
high period
Wait
State
Master1 SIF_CLK
Master2 SIF_CLK
Wired-AND SIF_CLK
Figure 36: Multi-Master Clock Synchronisation
After each transfer has completed, the status of the device must be checked to ensure that the data has been
acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any
point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost.
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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