JN516X Datasheet, PDF (35/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted
between transfers when required, to enable longer transfers to be performed.
When the device reset is active, all the SPI Master pins are configured as inputs with their pull-up resistors active.
The pins stay in this state until the SPI Master block is enabled, or the pins are configured for some other use.
Slave 0
Flash/
EEPROM
Memory
Slave 1
Us er
Def ine d
Slave 2
User
Def ine d
J^JN^N5⁵¹1⁶4^X 2
SPIMOSI
SPIC LK
SPIMISO
Figure 23: Typical JN516X SPI Peripheral Connection
The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN516x supports transfers at
selectable data rates from 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are
configurable. The clock phase determines which edge of SPICLK is used by the JN516x to present new data on the
SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured
appropriately for the SPI slave being accessed.
SPICLK
Polarity Phase
(CPOL) (CPHA)
0
0
0
1
1
0
1
1
Mode
0
1
2
3
Description
SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every
negative edge.
SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled
every positive edge.
Table 3: SPI Configurations
© NXP Laboratories UK 2013
JN-DS-JN516x v1.1 Production
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