JN516X Datasheet, PDF (44/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

12 Pulse Counters
Two 16-bit counters are provided that can increment during all modes of operation (including sleep). The first, PC0,
increments from pulses received on DIO1 or DIO4. The other pulse counter, PC1 operates from DIO5 or DIO8
depending upon the configuration. This is enabled under software control. The pulses can be de-bounced using the
32kHz clock to guard against false counting on slow or noisy edges. Increments occur from a configurable rising or
falling edge on the respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if
asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may
optionally be cascaded together to provide a single 32-bit counter, linked to any of the four DIO’s. The counters do
not saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value
is reached without software interaction so that pulses are not missed even if there is a long delay before an interrupt
is serviced or during the wakeup process.
The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When
using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be
used.
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013