JN516X Datasheet, PDF (46/94 Pages) NXP Semiconductors – IEEE802.15.4 Wireless Microcontroller

where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a
programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO,
one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The
status of the Transmit FIFO can be checked to see if it is empty, and if there is a character being transmitted. The
status of the Receive FIFO can also be checked, indicating if conditions such as parity error, framing error or break
indication have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives)
and if there is data held in the receive FIFO.
UART0 and UART1 can both be configured to use standard or alternative DIO lines, as shown in Table 5.
Additionally, UART0 can be configured to be used in 2-wire mode (where CTS0 and RTS0 are not configured), and
UART1 can be configured in 1-wire mode (where RXD1 is not configured). These freed up DIO pins can then be used
for other purposes.
Signal
CTS0
RTS0
TXD0
RXD0
TXD1
RXD1
DIO Assignment
Standard pins Alternative pins
DIO4
DIO12
DIO5
DIO13
DIO6
DIO14
DIO7
DIO15
DIO14
DIO11
DIO15
DIO9
Table 6: UART IO
.
Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART’s block negates
RTS when they receive FIFO that is about to become full. In some instances it has been observed that remote
devices that are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit
data. In these instances the data will be lost in a receive FIFO overflow.
13.1 Interrupts
Interrupt generation can be controlled for the UART’s block, and is divided into four categories:
• Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can
be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times.
• Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted.
• Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the
receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character
has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive
FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an
entire character.
• Modem Status: Generated when the CTS (Clear To Send) input control line changes.
13.2 UART Application
The following example shows the UART0 connected to a 9-pin connector compatible with a PC. As the JN516x
device pins do not provide the RS232 line voltage, a level shifter is used.
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JN-DS-JN516x v1.1 Production
© NXP Laboratories UK 2013