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MC68340AB16E Datasheet, PDF (82/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual | |||
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Freescale Semiconductor, Inc.
EXAMPLE B: A system uses error detection and correction on RAM contents. The
designer may:
1. Delay DSACKâ until data is verified and assert BERR and HALT simultaneously to
indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is
valid, assert DSACKâ (case 1).
2. Delay DSACKâ until data is verified and assert BERR with or without DSACKâ if
data is in error (case 3). This initiates exception processing for software handling of
the condition.
3. Return DSACKâ prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return DSACKâ prior to data verification; if data is invalid, assert BERR and HALT
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.
Table 3-4. DSACKâ, BERR, and HALT Assertion Results
Asserted on Rising
Edge of State
Case Control
Num
Signal
N
N+2
Result
1
DSACKâ
A
BERR
NA
HALT
NA
S
Normal cycle terminate and continue.
NA
X
2
DSACKâ
A
BERR
NA
HALT
A/S
S
Normal cycle terminate and halt; continue
NA
when HALT negated.
S
3
DSACKâ
NA/A
BERR
A
HALT
NA
X
Terminate and take bus error exception,
S
possibly deferred.
X
4
DSACKâ
A
BERR
NA
HALT
NA
X
Terminate and take bus error exception,
A
possibly deferred.
NA
5
DSACKâ
NA/A
BERR
A
HALT
A/S
X
Terminate and retry when HALT negated.
S
S
6
DSACKâ
A
BERR
NA
HALT
NA
X
Terminate and retry when HALT negated.
A
A
NOTES:
N â Number of the current even bus state (e.g., S2, S4, etc.)
A â Signal is asserted in this bus state
NA â Signal is not asserted in this state
X â Don't care
S â Signal was asserted in previous state and remains asserted in this state
MOTOROLA
MC68340 USERâS MANUAL
3-33
For More Information On This Product,
Go to: www.freescale.com
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