MC68340AB16E Datasheet, PDF (118/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
NOTE
An access to this register does not affect external space since
the cycle is not run externally.
Example code for accessing the MBAR is as follows:
Register D0 will contain the value of MBAR. MBAR can be read using the following code:
MOVE.L
MOVEC.L
LEA.L
MOVES.L
#7,D0
D0,SFC
$0003FF00,A0
(A0),D0
load D0 with the CPU space function code
load SFC to indicate CPU space
load A0 with the address of MBAR
load D0 with the contents of MBAR
Address $0003FF00 in CPU space (MBAR) will be loaded with the value $FFFFF001.
This value will set the base address of the internal registers to $FFFFF. MBAR can be
written to using the following code:
MOVE.L
MOVEC.L
LEA.L
MOVE.L
MOVES.L
#7,D0
D0,DFC
$0003FF00,A0
#$FFFFF001,D0
D0,(A0)
load D0 with the CPU space function code
load DFC to indicate CPU space
load A0 with the address of MBAR
load D0 with the value to be written into MBAR
write the value contained in D0 into MBAR
4.3.2 System Configuration and Protection Registers
The following paragraphs provide descriptions of the system configuration and protection
registers.
4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the
SIM40 configuration, can be read or written at any time.
MCR
$000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
FRZ1 FRZ0 FIRQ
0
0 SHEN1 SHEN0 SUPV 0
0
0
IARB3 IARB2 IARB1 IARB0
RESET:
0
1
1
0
0
0
0
0
1
0
0
0
1
1
1
1
Supervisor Only
Bits 15, 11, 10, 6–4—Reserved
FRZ1—Freeze Software Enable
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters are disabled, preventing interrupts from occurring during software
debug.
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters continue to run. See 4.2.7 Freeze for more information.
MOTOROLA
MC68340 USER’S MANUAL
4-21
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