MC68340AB16E Datasheet, PDF (299/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
currently active interrupt conditions. The interrupt enable register (IER) is programmable
to mask any events that can cause an interrupt.
7.1.5 Comparison of Serial Module to MC68681
The serial module is code compatible with the MC68681 with some modifications. The
following paragraphs describe the differences.
The programming model is slightly altered. The supervisor/user block in the MC68340
closely follows the MC68681. The supervisor-only block has the following changes:
• The interrupt vector register is moved from supervisor/user to supervisor only at a
new address.
• MR2A and MR2B are moved from a hidden address location to a location at the
bottom of the programming model.
The timer/counter is eliminated as well as all associated command and status registers.
Only certain output port pins are available.
There are no IP pins on the MC68340.
RxRTS and TxRTS are more automated on the MC68340.
The XTAL_RDY bit in the ISR should be polled until it is cleared to prevent an unstable
frequency from being applied to the baud rate generator. The following code is an
example:
if (XTAL_RDY==0)
begin
write CSR
end
else
begin
wait
jump loop
end
7.2 SERIAL MODULE SIGNAL DEFINITIONS
The following paragraphs contain a brief description of the serial module signals. Figure 7-
2 shows both the external and internal signal groups.
NOTE
The terms assertion and negation are used throughout this
section to avoid confusion when dealing with a mixture of
active-low and active-high signals. The term assert or assertion
indicates that a signal is active or true, independent of the level
represented by a high or low voltage. The term negate or
negation indicates that a signal is inactive or false.
7-4
MC68340 USER’S MANUAL
MOTOROLA
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