MC68340AB16E Datasheet, PDF (246/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
5.7.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table
indicates the number of clock periods needed for the processor to perform the specified
operation on the given addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
BCHG #, Dn
2
0
6(0/2/0)∗
BCHG Dn, Dm
4
0
6(0/1/0)
BCHG #, 〈FEA〉
1
2
8(0/2/1)∗
BCHG Dn, 〈FEA 〉
2
2
8(0/1/1)
BCLR #, Dn
2
0
6(0/2/0)∗
BCLR Dn, Dm
4
0
6(0/1/0)
BCLR #, 〈FEA〉
1
2
8(0/2/1)∗
BCLR Dn, 〈FEA 〉
2
2
8(0/1/1)
BSET #, Dn
2
0
6(0/2/0)∗
BSET Dn, Dm
4
0
6(0/1/0)
BSET #, 〈FEA〉
1
2
8(0/2/1)∗
BSET Dn, 〈FEA 〉
2
2
8(0/1/1)
BTST #, Dn
2
0
4(0/2/0)∗
BTST Dn, Dm
2
0
4(0/1/0)
BTST #, 〈FEA〉
1
0
4(0/2/0)∗
BTST Dn, 〈FEA 〉
2
0
8(0/1/0)
∗ = An # fetch EA time must be added for this instruction: 〈 FEA 〉 + 〈FEA 〉 + 〈OPER 〉
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MC68340 USER’S MANUAL
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