MC68340AB16E Datasheet, PDF (311/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

RxD
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDYA
Freescale Semiconductor, Inc.
C1
C2
C3
C4
C5
C6
C7
C8
C6, C7, C8 ARE LOST
CS
OVERRUN
(SR4)
RR
STATUS DATA
C1
C5
LOST
R R R R RR
STATUS DATA STATUS _DATA STATUS DATA
C2
C3
C4
RTS1
RESET BY COMMAND
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1
2. Timing shown for OPCR(4) = 1 and MR1(6) = 0
3. R = Read
4. CN = Received Character
Figure 7-8. Multidrop Mode Timing Diagram
A transmitted character from the master station consists of a start bit, a programmed
number of data bits, an address/data (A/D) bit flag, and a programmed number of stop
bits. The A/D bit identifies the type of character being transmitted to the slave station. The
character is interpreted as an address character if the A/D bit is set or as a data character
if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of the
MR1. The MR1 should be programmed before enabling the transmitter and loading the
corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream,
regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the
7-16
MC68340 USER’S MANUAL
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