MC68340AB16E Datasheet, PDF (176/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
5.5.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The VBR
contains the base address of a 1024-byte exception vector table, which consists of 256
exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are
reserved for user definition as interrupt vectors. Except for the reset vector which is two
long words, each vector in the table is one long word. Refer to Table 5-16 for information
on vector assignment.
Vector Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
Table 5-16. Exception Vector Assignments
Vector Offset
Dec
Hex
Space
0
000
SP
4
004
SP
8
008
SD
12
00C
SD
16
010
SD
20
014
SD
24
018
SD
28
01C
SD
32
020
SD
36
024
SD
40
028
SD
44
02C
SD
48
030
SD
52
034
SD
56
038
SD
60
03C
SD
64
040
SD
92
05C
96
060
SD
100
064
SD
104
068
SD
108
06C
SD
112
070
SD
116
074
SD
120
078
SD
124
07C
SD
128
080
SD
188
0BC
192
0C0
SD
232
0E8
236
0EC
SD
252
0FC
256
100
SD
1020
3FC
Assignment
Reset: Initial Stack Pointer
Reset: Initial Program Counter
Bus Error
Address Error
Illegal Instruction
Zero Division
CHK, CHK2 Instructions
TRAPcc, TRAPV Instructions
Privilege Violation
Trace
Line 1010 Emulator
Line 1111 Emulator
Hardware Breakpoint
(Reserved for Coprocessor Protocol Violation)
Format Error
Uninitialized Interrupt
(Unassigned, Reserved)
—
Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Trap Instruction Vectors (0–15)
—
(Reserved for Coprocessor)
—
(Unassigned, Reserved)
—
User-Defined Vectors (192)
MOTOROLA
MC68340 USER’S MANUAL
5-39
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