MC68340AB16E Datasheet, PDF (163/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support
operations on BCD numbers. The arithmetic operations on packed BCD numbers are add
decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal
with extend (NBCD). Table 5-9 is a summary of the BCD operations.
Instruction
ABCD
NBCD
SBCD
Table 5-9. Binary-Coded Decimal Operations
Operand
Syntax
Dn, Dn
– (An), – (An)
〈ea〉
Dn, Dn
– (An), – (An)
Operand Size
8
8
8
8
8
8
Operation
Source ₁₀ + Destination10 + X ⇒ Destination
0 – Destination10 – X ⇒ Destination
Destination10 – Source10 – X ⇒ Destination
5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return
instructions and conditional and unconditional branch instructions perform program control
operations. Table 5-10 summarizes these instructions.
Instruction
Bcc
DBcc
Scc
BRA
BSR
JMP
JSR
NOP
RTD
RTR
RTS
Table 5-10. Program Control Operations
Operand
Syntax
〈label〉
Dn , 〈label〉
〈ea〉
〈label〉
〈label〉
〈ea〉
〈ea〉
none
#〈 d〉
none
none
Operand Size
Operation
Conditional
8, 16, 32
If condition true, then PC + d ⇒ PC
16
If condition false, then Dn – 1 ⇒ PC;
if Dn ≠ (– 1), then PC + d ⇒ PC
8
If condition true, then destination bits are set to 1;
else destination bits are cleared to 0
Unconditional
8, 16, 32
PC + d ⇒ PC
8, 16, 32
SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
none
Destination ⇒ PC
none
SP – 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC
none
PC + 2 ⇒ PC
Returns
16
(SP) ⇒ PC; SP + 4 + d ⇒ SP
none
(SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒
SP
none
(SP) ⇒ PC; SP + 4 ⇒ SP
5-26
MC68340 USER’S MANUAL
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