MC68340AB16E Datasheet, PDF (362/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
TIMER 1
$600
$602
$604
$606
$608
$60A
$60C
$60E
$610
$612-$63F
TIMER 2
$640
$642
$644
$646
$648
$64A
$64C
$64E
$650
$652-$67F
FC 15
0
S MODULE CONFIGURATION REGISTER (MCR)
S
RESERVED
S
INTERRUPT REGISTER (IR)
S/U
CONTROL REGISTER (CR)
S/U
STATUS/PRESCALER REGISTER (SR)
S/U
COUNTER REGISTER (CNTR)
S/U
PRELOAD 1 REGISTER (PREL1)
S/U
PRELOAD 2 REGISTER (PREL2)
S/U
COMPARE REGISTER (COM)
S/U
RESERVED
Figure 8-11. Timer Module Programming Model
In the registers discussed in the following paragraphs, the numbers in the upper right-
hand corner indicate the offset of the register from the base address specified by the
module base address register (MBAR) in the SIM40. The first number is the offset for
timer 1; the second number is the offset for timer 2. The numbers on the top line of the
register represent the bit position in the register. The register contains the mnemonic for
the bit. The value of these bits after a hardware reset is shown below the register. The
access privilege is shown in the lower right-hand corner.
NOTE
A CPU32 RESET instruction will not affect the MCR, but will
reset all other registers in the timer modules as though a
hardware reset occurred.
The term 'timer' is used to reference either timer 1 or timer 2, since the two are functionally
equivalent.
8.4.1 Module Configuration Register (MCR)
The MCR controls the timer module configuration. This register can be either read or
written when the module is enabled and is in the supervisor state. The MCR is not
affected by a CPU32 RESET instruction.
MCR
$600, $640
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STP FRZ1 FRZ0
0
0
0
0
0
SUPV
0
0
0 IARB3 IARB2 IARB1 IARB0
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Supervisor Only
8-18
MC68340 USER’S MANUAL
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