MC68340AB16E Datasheet, PDF (233/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
12 34 56 7 8 90 12 3 4
CLOCK
BUS 1 PRE-
CONTROLLER FETCH
INSTRUCTION
CONTROLLER
MOVEQ
EXECUTION MOVEQ
TIME #7,D1
2 PRE-
FETCH
CMP
CMP
D1,D0
OFFSET
CALC
3 PRE-
FETCH
NOT
TAKEN
BLE.B NOT TAKEN
4 PRE-
FETCH
MOVE TO
(A0)
WRITE
FOR 4
WRITE
FOR 4
MOVE.L D1,(AO)
Figure 5-35. Example 2—Branch Not Taken
5.7.2.3 TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows
how to use negative tail figures for branches and other change-of-flow instructions. In this
example, bus speed is assumed to be four clocks per access. Instruction three is at the
branch destination.
Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum
branch instruction time to be three bus cycles. The negative tail is a reminder that an extra
two clocks are available for prefetching a third word on a fast bus; on a slower bus, there
is no extra time for the third word.
Instructions
MOVEQ
BRA.W
MOVE.L
#7, D1
FARAWAY
D1, D0
12 34 56 7 8 90 12 3 4 5 67 8 9
CLOCK
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
EXECUTION
TIME
BRANCH OFFSET
MOVEQ
MOVEQ #7,D1
FETCH MOVE.L
OFFSET
CALC
TAKEN
BRA.W FARAWAY
FETCH NEXT
INSTRUCTION
TAKEN
Figure 5-36. Example 3—Branch Negative Tail
PREFETCH
MOVE
TO D0
MOVE.L D1,D0
5-96
MC68340 USER’S MANUAL
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