MC68340AB16E Datasheet, PDF (366/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
POT2–POT0—Prescaler Output Tap
If PCLK is set, these bits encode which of the prescaler's output taps act as the counter
clock. A division of the selected clock is applied to the counter as listed in Table 8-4.
Table 8-4. POT Encoding
POT2
0
0
0
1
1
1
1
0
POT1
0
1
1
0
0
1
1
0
POT0
1
0
1
0
1
0
1
0
Division of
Selected Clock
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Divide by 256
MODE2–MODE0—Operation Mode
These bits select one of the eight modes of operation for the timer as listed in Table 8-5.
Refer to 8.3 Operating Modes for more information on the individual modes.
MODE2
0
0
0
0
1
1
1
1
Table 8-5. MODEx Encoding
MODE1
0
0
1
1
0
0
1
1
MODE0
0
1
0
1
0
1
0
1
OPERATION MODE
Input Capture/Output Compare
Square-Wave Generator
Variable Duty-Cycle Square-Wave Generator
Variable-Width Single-Shot Pulse Generator
Pulse-Width Measurement
Period Measurement
Event Count
Timer Bypass (Simple Test Mode)
OC1–OC0—Output Control
These bits select the conditions under which TOUTx changes (see Table 8-6). These
bits may have a different effect when in the input capture/output compare mode.
Caution should be used when modifying the OC bits near timer events.
Table 8-6. OCx Encoding
OC1
0
0
1
1
OC0
0
1
0
1
TOUTx MODE
Disabled
Toggle Mode
Zero Mode
One Mode
8-22
MC68340 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA