MC68340AB16E Datasheet, PDF (390/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
VCCSYN
MC68340
XFC
VCCSYN
0.1 µF ¹
0.1 µF
0.01 µF
NOTE 1: Must be a low-leakage capacitor.
Figure 10-4. XFC and V_CCSYN Capacitor Connections
10.1.2 Reset Circuitry
Because it is optional, reset circuitry is not shown in Figure 10-1. The MC68340 holds
itself in reset after power-up and asserts RESET to the rest of the system. If an external
reset pushbutton switch is desired, an external reset circuit is easily constructed by using
open-collector cross-coupled NAND gates to debounce the output from the switch.
10.1.3 SRAM Interface
The SRAM interface is very simple when the programmable chip selects are used.
External circuitry to decode address information and circuitry to return data and size
acknowledge (DSACK≈) is not required. However, external ICs are required to provide
write enables for the high and low bytes of data.
A15-A1
SIZ0
A0
AS
MC68340
R/W
D15-D0 ^CS
UWE
LWE
....
....
MCM6206-35
R/W
CE
E
.. ^..
D7-D0
... ^.
... ^.
MCM6206-35
R/W
CE
E
... ^.
D15-D8
Figure 10-5. SRAM Interface
The SRAM interface shown in Figure 10-5 is a two-clock interface at 16.78-MHz operating
frequency. The MCM6206C-35 memories provide an access time of 15 ns when the chip
enable (E) input is low. If buffers are required to reduce signal loading or if slower and less
expensive memories are desired, a three-clock cycle can be used. In the circuit shown in
Figure 10-5, additional memories can be used provided the MC68340 specification for
MOTOROLA
MC68340 USER’S MANUAL
10-3
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