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MC68340AB16E Datasheet, PDF (258/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual | |||
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Freescale Semiconductor, Inc.
CLKOUT
CPU CYCLE
S0
S2
S4
A31âA0
DMA READ
S0
S2
S4
DMA READ
S0
S2
S4
CPU CYCLE
S0
FC3âFC0
SIZ1âSIZ0
AS
DS
R/W
D15âD0
DSACKx
DREQx
DONEx
.(...INPUT)
DACKx
DONEx
(OUTPUT)
NOTE:
1. Timing to generate more than one DMA request.
2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
3. DREQx must be asserted while DACKx is asserted and meet the setup and hold times for
more than one DMA transfer to be recognized.
Figure 6-5. Single-Address Read Timing (External Burst)
6-8
MC68340 USERâS MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
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